A. Field of the Invention
The present invention relates to a power MOS semiconductor device having a trench type insulated gate. Further in detail, the invention relates to a vertical power MOS semiconductor device having a trench type insulated gate structure with a trench, a gate insulator film and a control electrode, the trench being formed in a semiconductor substrate in a stripe-like surface pattern, the gate insulator film being formed on the sidewall surface of the trench and the control electrode being buried in the trench with the gate insulator film interposed between. In the structure, first conductivity type regions and second conductivity type regions are alternately formed on the surface of the substrate in the longitudinal direction of the trench.
B. Description of the Related Art
In recent years, in compliance with requirements for downsizing and performance enhancement in power source equipment in the field of power electronics, efforts have been concentrated on a power semiconductor device to improve the performance thereof in obtaining a high breakdown voltage, a high current capacity and, along with this, a low power loss, a high breakdown blocking capability and a high operation speed. As a power semiconductor device capable of obtaining such a high current capacity and a low power loss, many vertical MOS semiconductor devices are used which are provided with trench type insulated gates. A power MOS semiconductor device is driven by a MOS (Metal/Oxide film/Semiconductor) gate. Two types of MOS gate structure are well known, i.e., planar MOS gate structures and trench MOS gate structures. A planar MOS gate structure has a MOS gate provided in plane on the surface of a semiconductor substrate and a trench MOS gate structure has a MOS gate formed by being buried in a trench vertically formed to the surface of a semiconductor substrate. In recent vertical semiconductor devices, a so-called vertical and trench type MOS semiconductor device having a trench MOS gate structure has become a focus of attention because its structure makes it easy to obtain low on-resistance characteristics.
With respect to a vertical trench type MOS semiconductor device having such a trench type insulated gate structure, a vertical and trench type IGBT (Insulated Gate Bipolar Transistor) has already been publicly known as a device that enables the realization of both low on-resistance and high breakdown voltage (JP-A-2000-228519 (FIG. 6 and FIG. 7)). The vertical and trench type IGBT has a trench type insulated gate structure in which a gate electrode is buried in each trench formed in stripes or linearly with an insulator film interposed between. Moreover, p-type channel regions and n-type semiconductor substrate regions form a pattern of alternately appearing on the surface of a semiconductor substrate between the trenches in the direction along the trenches.
In order to realize secured load short circuit blocking capability, reduction in on-voltage and reduction in input capacitance of a trench gate IGBT, a device is known in which p-type base regions are formed in a direction perpendicular to the direction of a trench gate and in stripes, and each of unit cells of the trench gate IGBT is formed to have such an approximately uniform channel length as to be equal to or shorter than that of related trench type IGBTs (see the abstract of JP-A-2001-274400).
An example of a structure of such a vertical and trench type IGBT is shown in a perspective view in FIG. 10, with cross sectional views in FIG. 11-1, FIG. 11-2, FIG. 11-3 and a plan view in FIG. 12. Furthermore, for making an explanation with comparison, a principal part of a related planar type IGBT is shown in a cross sectional view in FIG. 17. The structures and operations of the related IGBTs will be explained with reference to the above drawings. In the related vertical and trench type IGBT, on one of the principal surfaces (hereinafter referred to as the top surface) of n−-type semiconductor substrate 111, p-type channel region 112 is selectively formed and, on the other principal surface (hereinafter referred to as the bottom surface), n+-type FS (field stop) layer 150 and p-type collector layer 151 are formed. Moreover, a number of trenches 113 with a surface pattern that is orthogonal to p-type channel region 112 are formed from the top surface of n−-type semiconductor substrate 111 to a depth reaching an n−-type drain layer as a region in n−-type semiconductor substrate 111 through p-type channel region 112. The inner surface of trench 113 is covered with gate oxide film 114. Further to the inside of trench 113, gate electrode 115 of a material such as conductive polycrystalline silicon is buried. On the surface of channel region 112 between trenches 113 adjacent to each other, p+-type body region 117 is provided in the approximate middle thereof. Adjacent to p+-type body region 117 and trench 113, an n+-type emitter region 116 is provided. On gate electrode 115, insulator layer 118 is disposed and metal electrode 119 of a metal such as aluminum is provided on the whole surface of the unit cell region of the IGBT with insulator layer 118 insulating and separating gate electrode 115 from metal electrode 119. Moreover, an arrangement is provided so that metal electrode 119 makes ohmic contact with the surfaces of n+-type emitter region 116 and p+-type body region 117 in a contact region provided as a region including the surfaces of both of a portion of n+-type emitter region 116 and a portion of p+-type body region 117. Collector electrode 122 is then formed, by which a vertical IGBT in a wafer stage is completed. (In FIG. 17, element numbers correspond to those in FIG. 10, with the exception of the first digit. For example, stopping layer 150 in FIG. 10 is denoted as stopping layer 250 in FIG. 17.)
In the thus arranged vertical and trench type IGBT, by applying a voltage above a specified threshold value to gate electrode 115, an n-type inversion layer (not shown) is formed on the surface layer of p-type channel region 112 along the sidewall of trench 113, by which current paths are formed as shown by arrows in FIGS. 11-1 to 11-3. This makes the vertical and trench type IGBT in a turned-on state between the emitter and the collector. Moreover, by bringing the voltage applied to gate electrode 115 to below a specified threshold value, the n-type inversion layer on p-type channel region 112 along the sidewall of trench 113 disappears, by which the current paths disappear to make the vertical and trench type IGBT in a turned-off state between the emitter and the collector. Furthermore, along trench 113, vertical (in the direction perpendicular to the principal surfaces of the substrate: FIG. 11-1) and lateral (in the direction in parallel to the principal surfaces of the substrate: FIG. 11-2) current paths (shown by arrows) are formed. Thus, compared with a publicly known planar type or trench type vertical IGBT, the areas of the current paths are remarkably expanded. In addition, between trenches 113 on the substrate surface side, minority carriers are stored in the surface region so that n−-type semiconductor substrate 111 appears to offer the advantage of reducing on-resistance. In such a related vertical trench type IGBT, the presence of a rough correlation was observed between the designed breakdown voltage and the current density. This was such that a current density was 200 to 250 A/cm2 in a 600 V class IGBT, 100 to 150 A/cm2 in a 1200 V class IGBT and 40 to 60 A/cm2 in a 2500 V class IGBT, which was such a correlation as to be roughly expressed as VI=150 kVA.
However, in the arrangement of the vertical trench type IGBT shown in FIG. 10, a problem is present in low turn-off capability. It was found that the problem is due to the following cause. This will be explained by using FIG. 10, FIG. 11-1 to FIG. 11-3 and FIG. 12 again. FIG. 11-1 to FIG. 11-3 are cross sectional views taken on line A-A, line B-B and line C-C, respectively, of FIG. 10. As was explained for the related background art, in the arrangement of the vertical and trench type IGBT shown in FIG. 10, two kinds of current paths are formed with current paths of a so-called trench type IGBT (shown by arrows) as shown in FIG. 11-1, the cross sectional view taken on line A-A of FIG. 10, and the paths of the currents (shown by arrows) flowing in the lateral direction (in the direction in parallel to the principal surface of the substrate) along the sidewall of the trench as shown in FIG. 11-2, the cross sectional view taken on line B-B of FIG. 10. Of the two kinds of current paths, the current paths of electrons (solid line arrows) flowing in the lateral direction along the sidewall of the trench are rather similar to the electron current paths (solid line arrows) in a planar IGBT shown in FIG. 17. However, compared with the planar IGBT shown in FIG. 17, in which hole current paths are shown by broken lines and electron current paths are in the same plane, in the arrangement of the trench type IGBT shown in FIG. 11-2, electron current paths (solid line arrows) and hole current paths are not present in the same plane. In this respect, the trench type IGBT is different from the planar IGBT. The hole currents, as shown by solid line arrows in FIG. 12 being a plan view in which the trench type IGBT shown in a perspective view shown in FIG. 10 is viewed from above, are to flow from the region in the cross section along the line B-B of FIG. 11-2 toward the region in the cross section along the line C-C of FIG. 11-3. In other words, it can be said that the paths of the hole currents become current paths such that the hole currents flow in from the trench sidewall along a contact plane of an emitter electrode and a semiconductor layer. Therefore, the hole currents are to concentrate in each of encircled regions in FIG. 12 and to pass below the n+-type emitter region 116. The hole current is equivalent to a base current in an NPN transistor formed with n+-type emitter region 116/p-type channel region 112/n−-type semiconductor substrate 111 (Note: The layer arrangement is expressed by combining constituents with the “/” marks, in which the constituents are present in the described order while being separated with the “/” marks). It was found that the concentration of the hole current makes the operation of the NPN transistor easy to result in making the operation of a parasitic thyristor of the IGBT easy which thyristor is formed with n+-type emitter region 116/p-type channel region 112/n−-type semiconductor substrate 111/p-type collector layer 151, which makes the turning-off of the IGBT uncontrollable and degrades turn-off capability.
Furthermore, in a power semiconductor device, applied to a motor driving inverter of an electric vehicle or a hybrid vehicle and used by double-sided cooling, its high cooling efficiency makes it desirable to use the device at a further higher current density. Namely, in a 1200 V class device, it is desired that the device can be used with a current density of 300 to 500 A/cm2, which is higher than the current density of 100 to 150 A/cm2 of the above explained related vertical trench type IGBT. When the device is applied under such a high current density condition, there is a problem with the arrangement of the related vertical and trench type IGBT shown in the above FIG. 10 in compatibility between the use at a high current density and reduction in an on-voltage. This problem will be explained with reference to FIG. 11-1 to FIG. 12. In general, a saturation current Isat is expressed by the following expression (1) as
                              I          sat                =                              1                          (                              1                -                                  α                  PNP                                            )                                ⁢                                                    μ                                  n                  ⁢                                                                          ⁢                  s                                            ⁢                              C                ox                            ⁢              Z                                      2              ·                              L                CH                                              ⁢                                    (                                                V                  GE                                -                                  V                                      GE                    ⁡                                          (                      th                      )                                                                                  )                        2                                              (        1        )            
where αPNP is a current-amplification factor, μns is electron mobility in an inversion layer, Cox is capacitance of a gate oxide layer, LCH is a channel length, VGE is a gate bias voltage, VGE(th) is a gate threshold voltage and Z is a total emitter width. To ensure design freedom and sacrificing no other characteristics, it is desirable to adjust the saturation current Isat by changing only the total emitter width Z in the above expression (1).
More particularly, it is desirable to allow the saturation current Isat to increase by increasing the total emitter width Z. Here, the total emitter width is the sum of the widths (lengths) of the sections of n+-type emitter region 116, with each of which sections n+-type emitter region 116 in a unit cell region between trenches 113 makes contact with trench 113, about the total cells in a unit area. In the following, although the emitter width will be sometimes referred to as the emitter length, both are the same.
As was shown in the related background art, in the arrangement of the vertical trench type IGBT shown in the above FIG. 10, two kinds of current paths are formed. One is the current path shown in FIG. 11-1 in which currents flow in channel region 112 on the sidewall of the so-called trench type IGBT from emitter region 116 in the direction of the thickness of the substrate along the sidewall of the trench. The other is the current path shown in FIG. 11-3 in which currents flow in the channel region 112 along the sidewall of the trench in the lateral direction in parallel with the principal surface of the substrate. For achieving a low on-voltage, it is necessary to secure current paths in which currents flow in the lateral direction in parallel with the principal surface of the substrate along the sidewall of the trench.
However, only with the total emitter width widened according to the expression (1) for increasing the saturation current while keeping the arrangement of the vertical trench type IGBT shown in the above FIG. 10, it was found that the emitter region is made to come naturally closer to the end of the channel region in the longitudinal direction of the trench to make it impossible to form the current paths of the currents flowing on the sidewall of the trench in the lateral direction and to therefore make it difficult to lower the on-voltage with a high current density.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above. The invention was made in view of the foregoing problem and an object of the invention is to provide a vertical and trench type insulated gate MOS semiconductor device which can achieve lowered on-resistance and enhancement in turn-off capability.